Design Flow
The basic flow for using VHDL and synthesis to design an ASIC or complex FPGA is shown below. Iteration around the design flow is necessary, but is not shown here. Also, the design flow must be modified according to the kind of device being designed and the specific application.
1 System analysis and specification
2 System partitioning
2.1 Top level block capture
2.2 Block size estimation
2.3 Initial floorplanning
3 Block level design. For each block:
3.1 Write Register Transfer Level VHDL
3.2 Synthesis coding checks
3.3 Write VHDL test bench
3.4 VHDL simulation
3.5 Write synthesis scripts - constraints, boundary conditions, hierarchy
3.6 Initial synthesis - analysis of gate count and timing
4 Chip integration. For complete chip:
4.1 Write VHDL test bench
4.2 VHDL simulation
4.3 Synthesis
4.4 Gate level simulation
5 Test generation
5.1 Modify gate level netlist for test
5.2 Generate test vectors
5.3 Simulate testable netlist
6 Place and route (or fit) chip
7 Post layout simulation and timing analysis
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